Field of the Invention
The present invention relates to a novel binary latch comprising a master flip-flop and a slave latch.
Description of Related Art
Binary latches are commonly built up with edge-triggered elements; examples are master-only or master and slave flip-flop circuits. Such binary latches have been used in chip architecture for a long time and are present in large quantities for example in registers or state machine design. They have the disadvantage that testing the logic of a circuit containing these latches is rather complex and has to be performed with functional vectors provided by the chip designer.
Another common way to build latches is based on the level sensitive scan design (LSSD) known in the state of the art, which allows testing in an easier way. Such binary latches combine an LSSD master and LSSD slave to a shift register latch pair (SRL). In order to make an LSSD latch perform like an edge-triggered element a clock splitter (CLKSPL) has to be added as shown in FIG. 3. For LSSD testing the SRL is clocked in a different way than in normal operation mode. In the example shown in FIG. 3 an LSSD_A testclock for copying the scan input (Scan Input) into the master L1 latch, an LSSD_C testclock for copying the data (Data) into the master L1 latch and an LSSD_B testclock for copying the master content of the master L1 latch into the slave latch L2 has to be established on the chip besides the devices to provide the system clock (System Clock). As the system clock is the only one relevant in normal operation mode the application needs a large extra overhead of clock-splitters and testclock trees, only to make the product LSSD testable. The three LSSD testclock trees are mostly not well skew-managed, which makes it often necessary to apply the tests with a lower frequency.